F81867
Fintek Used Only Register 1 ⎯ Offset 07h
Bit
Name
R/W Reset
R/W 5VSB
Default
Description
7-0
Reserved
1
This byte is fintek used only, don’t change the default value
Fintek Used Only Register 2 ⎯ Offset 0Fh
Bit
Name
R/W Reset
Default
Description
7-0
Reserved
-
-
-
This byte is fintek used only, don’t write to this byte.
7.20.8
Hardware Monitor μC Side Register (base address 0x2000, 256 byte)
7.18.8.1
Temperature Setting
Configuration Register 1 ⎯ Offset 01h
Bit
7-3
2
Name
R/W Reset
Default
Description
Reserved
Reserved
0h
-
0
0
Hardware monitor function power down.
POWER_DOWN R/W
5VSB
Set one to enable startup of fan monitoring operations; a zero
puts the part in standby mode.
Set one to enable startup of temperature and voltage monitoring
operations; a zero puts the part in standby mode.
1
0
FAN_START
V_T_START
R/W
R/W
5VSB
5VSB
1
1
Protection Mode Configuration Register ⎯ Offset 02h
Bit
Name
R/W Reset
Default
Description
Dummy register.
7
Reserved
R/W
-
0
0: Disable case open event output via BEEP.
6
CASE_BEEP_EN R/W
5VSB
0
0
1: Enable case open event output via BEEP.
00: The OVT# will be low active level mode.
01: The OVT# will be low pulse mode.
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
Dummy register.
5-4
OVT_MODE
R/W
5VSB
3
2
Reserved
R/W
R/W
-
0
0
0: Disable case open event output via PME.
CASE_SMI_EN
5VSB
1: Enable case open event output via PME.
00: The ALERT# will be low active level mode.
01: The ALERT# will be high active level mode.
10: The ALERT# will indicate by 1Hz LED function.
11: The ALERT# will indicate by (400/800HZ) BEEP output.
1-0
ALERT_MODE R/W
5VSB
0
Case Open Status Register ⎯ Offset 03h
Bit
Name
R/W Reset
Default
Description
Reserved
7-1
Reserved
R/W
R/W
-
0
Case open event status, write 1 to clear if case open event
cleared. (This bit is powered by VBAT.)
0
CASE_STS
VBAT
0
217
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
