F81867
Configuration Register 2⎯ Offset 04h
Bit
7
Name
Reserved
BIAS_EN
Reserved
S3_HM_EN
R/W Reset
Default
Description
Reserved
-
-
-
0
-
6
R/W
R/W
R/W
5VSB
-
Reserved for Fintek use only
Reserved
5-1
0
5VSB
0
Set 1 to enable monitoring at S3 state.
TSI Control Register1 ⎯ Offset 08h
Bit
Name
R/W Reset
Default
Description
AMD TSI or Intel IBex slave address
Reserved
7-1
TSI_ADDR
R/W
-
5VSB
-
26h
0
Reserved
-
TSI Control Register2 ⎯ Offset 09h
Bit
Name
R/W Reset
Default
Description
Address for I2C master to use a block write command
Reserved
7-1
SMB_ADDR
R/W
-
5VSB
-
0
0
Reserved
-
Configuration Register 3 ⎯ Offset 0Ah
Bit
Name
R/W Reset
Default
Description
0: disable the T2 beta compensation.
1: enable the T2 beta compensation.
0: disable the T1 beta compensation.
1: enable the T1 beta compensation.
This bit is used to select AMD TSI or Intel IBEX when TSI_EN is
set to 1.
7
6
BETA_EN2
R/W
R/W
5VSB
5VSB
0
BETA_EN1
0
5
4
INTEL_SEL
R/W
5VSB
1
0
0: Select AMD
1: Select Intel
MXM_MODE
R/W LRESET#
Reserved.
PECI (VTT) voltage selection.
00: VTT is 1.23V
3-2
VTT_SEL
R/W
R/W
5VSB
0
01: VTT is 1.13V
10: VTT is 1.00V
11: VTT is 1.00V
Set this bit 1 to enable AMD TSI or Intel IBEX function
1
0
TSI_EN
5VSB
0
0
Set this bit 1 to enable Intel PECI function
PECI_EN
R/W LRESET#
218
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
