F81867
00: PWM1 clock source is group 0 clock.
01: PWM1 clock source is group 1 clock.
10: PWM1 clock source is group 2 clock.
11: PWM1 clock source is group 3 clock.
3-2
1-0
PCS1
PCS0
R/W 5VSB
R/W 5VSB
00
00
00: PWM0 clock source is group 0 clock.
01: PWM0 clock source is group 1 clock.
10: PWM0 clock source is group 2 clock.
11: PWM0 clock source is group 3 clock.
PWM Clock Gate Register ⎯ Offset 08h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
-
Reserved.
0: Enable PWM3 clock.
1: Disable PWM3 clock.
3
2
1
0
PCSGR3
PCSGR2
PCSGR1
PCSGR0
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0: Enable PWM2 clock.
1: Disable PWM2 clock.
0
0
0
0: Enable PWM1 clock.
1: Disable PWM1 clock.
0: Enable PWM0 clock.
1: Disable PWM0 clock.
PWM Type Register ⎯ Offset 09h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
-
Reserved.
0: Open drain.
1: Push pull.
3
2
1
0
PWM3_TYPE
PWM2_TYPE
PWM1_TYPE
PWM0_TYPE
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0: Open drain.
1: Push pull.
0
0
0
0: Open drain.
1: Push pull.
0: Open drain.
1: Push pull.
PWM Enable Register ⎯ Offset 0Ah
Bit
7
Name
R/W Reset Default
Description
SOFT_RST
Reserved
W
-
5VSB
-
0
-
Write “1” to software reset PWM block.
Reserved.
6-1
0: Disable PWM. All clocks will be disabled.
1: Enable PWM.
0
PCCE
R/W 5VSB
0
PWM0 Duty Control Register ⎯ Offset 10h
Bit
Name
R/W Reset Default
Description
The duty cycle of PWM0 will be (DCR0/255)*100%. Set 0 to force stop and
0xFF to force 100% duty.
7-0
DCR0
R/W 5VSB
0
213
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
