F81867
TSI Temperature 0 – Offset E0h
Bit
Name
R/W Reset Default
Description
This is the AMD TSI reading if AMD TSI enable.
And will be highest temperature among CPU, MCH and PCH if
Intel temperature interface enable. The range is 0~255ºC. To
access this byte, MCH_BANK_SEL must set to “0”.
This byte is used as multi-purpose:
TSI_TEMP0
R/W 5VSB
-
7. The received data of receive protocol.
7-0
8. The first received byte of read word protocol.
9. The 10th received byte of read block protocol.
10. The sent data for send byte protocol and write byte
protocol.
I2C_DATA0
R/W 5VSB
8’h00
11. The first send byte for write word protocol.
12. The first send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 1 – Offset E1h
Bit
Name
R/W Reset Default
Description
This is the high byte of Intel temperature interface PCH reading.
The range is 0~255ºC.
TSI_TEMP1
R
5VSB
-
To access this byte, MCH_BANK_SEL should be set to “0”.
This byte is used as multi-purpose:
7-0
5. The second received byte of read word protocol.
6. The 11th received byte of read block protocol.
7. The second send byte for write word protocol.
8. The second send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
I2C_DATA1
R/W 5VSB
8’h00
TSI Temperature 2 Low Byte – Offset E2h
Bit
Name
R/W Reset Default
Description
This is the low byte of Intel temperature interface CPU reading.
The reading is the fraction part of CPU temperature. Bit 0
indicates the error status.
7-0
TSI_TEMP2_LO
R
5VSB
-
0: No error.
1: Error code.
To access this byte, MCH_BANK_SEL should be set to “0”.
220
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
