F81867
Host to EC Data Register ⎯ Offset 01h
Bit
Name
R/W Reset Default
Description
This is the data written by host to communicate with μC. The type of this byte
7-0
H2E_DATA
R
5VSB
0x00 is determined by H2E_DATA_TYPE. μC reads this byte and check the
H2E_DATA_TYPE to decide what action should be done.
EC to Host Data Register ⎯ Offset 02h
Bit
Name
R/W Reset Default
Description
This is the data written by μC to communicate with host. The type of this byte
7-0
E2H_DATA
R/W 5VSB
0x00 is determined by E2H_DATA_TYPE. Host reads this byte and check the
E2H_DATA_TYPE to decide what action should be done.
Port 80 WDT Control Register ⎯ Offset 03h
Name R/W Reset Default
Bit
7
Description
This bit is written by μC to indicate a timeout status. Host could write “1” to
this bit to clear status.
P80_WDT_TO_ST R/W 5VSB
0
0
6
P80_WDT_EN
P80_WDT_UNIT
P80_WDT_PIN
R
R
R
5VSB
5VSB
5VSB
Host write “1” to this bit to inform μC to enable Port 80 WDT function.
Written by host to define the time unit. Ex.
00: 100ms.
01: 1 second.
10: 1 minute.
11: 1 hour.
5-4
3-0
0
0
Written by host to define the pins to assert WDT reset signal.
Port 80 WDT Time Register ⎯ Offset 04h
Bit
Name
R/W Reset Default
Description
7-0
P80_WDT_TIME
R
5VSB 0xff Written by host to define the time count of WDT.
Port 80 WDT Code Register ⎯ Offset 05h
Bit
Name
R/W Reset Default
Description
7-0
P80_WDT_CODE
R
5VSB 0xff Written by host to define the code to start WDT.
Port 80 Code Register ⎯ Offset 06h
Bit
Name
R/W Reset Default
Description
7-0
P80_CODE
R
5VSB
0xff This byte record the data write to Port 80 address (default 0x0080).
Port 80 Last Code Register ⎯ Offset 07h
Name R/W Reset Default
Bit
Description
μC could write the last data of 80 port into this byte to record the last code
during current boot up.
7-0
P80_LAST_CODE R/W 5VSB
0xff
Port 80 Base Address High Byte Register ⎯ Offset 10h
Bit
Name
R/W Reset Default
Description
7-0
P80_BASE_H
R/W 5VSB 0x00 The 80 port base address high byte.
215
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
