F81867
This is the 12th byte of the block read protocol.
I2C_DATA2
R/W 5VSB
8’h00 This byte is also used as the 3rd byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 2 High Byte – Offset E3h
Bit
Name
R/W Reset Default
Description
This is the high byte of Intel temperature interface CPU reading.
The reading is the decimal part of CPU temperature.
To access this byte, MCH_BANK_SEL should be set to “0”.
This is the 13th byte of the block read protocol.
TSI_TEMP2_HI
R
5VSB
-
7-0
I2C_DATA3
R/W 5VSB
8’h00 This byte is also used as the 4th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 3 – Offset E4h
Name
Bit
R/W Reset Default
Description
This is the high byte of Intel temperature interface MCH reading.
The range is 0~255ºC.
TSI_TEMP3
I2C_DATA4
R
5VSB
-
To access this byte, MCH_BANK_SEL should be set to “0”.
This is the 14th byte of the block read protocol.
7-0
R/W 5VSB
8’h00 This byte is also used as the 5th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 4 – Offset E5h
Name
Bit
R/W Reset Default
Description
This is the high byte of Intel temperature interface DIMM0
reading. The range is 0~255ºC.
TSI_TEMP4
I2C_DATA5
R
5VSB
-
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 15th byte of the block read protocol.
R/W 5VSB
8’h00 This byte is also used as the 6th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 5 – Offset E6h
Name
Bit
R/W Reset Default
Description
This is the high byte of Intel temperature interface DIMM1
reading. The range is 0~255ºC.
7-0
TSI_TEMP5
R
5VSB
-
To access this byte, MCH_BANK_SEL should be set to “0”.
221
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
