F81867
PWM1 Duty Control Register ⎯ Offset 11h
Bit
Name
R/W Reset Default
Description
The duty cycle of PWM1 will be (DCR1/255)*100%. Set 0 to force stop and
0xFF to force 100% duty.
7-0
DCR1
R/W 5VSB
0
PWM2 Duty Control Register ⎯ Offset 12h
Bit
Name
R/W Reset Default
Description
The duty cycle of PWM2 will be (DCR2/255)*100%. Set 0 to force stop and
0xFF to force 100% duty.
7-0
DCR2
R/W 5VSB
0
PWM3 Duty Control Register ⎯ Offset 13h
Bit
Name
R/W Reset Default
Description
The duty cycle of PWM3 will be (DCR3/255)*100%. Set 0 to force stop and
0xFF to force 100% duty.
7-0
DCR3
R/W 5VSB
0
7.20.4
7.20.5
7.20.6
μC Side SRAM1 Register (Base Address 0x1300, 256 bytes)
Offset 00h ~ FFh, 256 bytes SRAM accssed by μC, SRAM Powered by I_VSB3V
μC Side SRAM2 Register (Base Address 0x1400, 256 bytes)
Offset 00h ~ FFh, 256 bytes SRAM accssed by μC, SRAM powered by I_VSB3V
Host to EC Control μC Side Register (Base Address 0x1500, 256 bytes)
Host to EC Control Register ⎯ Offset 00h
Bit
Name
R/W Reset Default
Description
0: 0x80 port will decode all 16-bit address.
7
P80_DEC_RANGE R/W 5VSB
0
0
1: 0x80 port will decode 15-bit address, ignore LSB.
0: Disable EC to Host interrupt.
1: Assert to Host (if SIRQ channel is enabled) when EC to Host data
available which is set by writing E2C_DATA register (offset 02h). Also assert
SMI event to PME block when this bit is enabled.
6
E2H_INT_EN
R/W 5VSB
This bit is set when μC write data to offset 02h and is clear by host reading
the corresponding data. (H2E bass + 02h)
5
4
E2H_DATA_AVAIL R/W 5VSB
H2E_DATA_AVAIL 5VSB
0
0
This bit is set when host write data to offset 01h and is clear by μC reading
the corresponding data. (E2H bass + 01h)
R
3-2
1-0
E2H_DATA_TYPE R/W 5VSB
H2E_DATA_TYPE 5VSB
0
0
User defined register to define the type of EC to host data (offset + 02h)
User defined register to define the type of host to EC data (offset + 01h)
R
214
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
