F81867
Set “1” to enable write protect for RTC RAM index
0xC0 ~ 0xCF.
4
3
2
1
0
RTC_WR_DIS_4
RTC_WR_DIS_3
RTC_WR_DIS_2
RTC_WR_DIS_1
RTC_WR_DIS_0
R/W
R/W
R/W
0
0
0
0
0
5VSB
5VSB
5VSB
Set “1” to enable write protect for RTC RAM index
0xB0 ~ 0xBF.
Set “1” to enable write protect for RTC RAM index
0xA0 ~ 0xAF.
Set “1” to enable write protect for RTC RAM index
0x90 ~ 0x9F.
R/W 5VSB
R/W 5VSB
Set “1” to enable write protect for RTC RAM index
0x80 ~ 0x8F.
Software Reset 1 Register ⎯ Offset 10h
Bit
7
Name
RSMFI
Reserved
RINTC
R/W Reset Default
Description
Write “1” to assert a software reset to SPI block.
Reserved.
W
-
-
-
-
-
-
-
-
-
-
-
-
-
6-5
4
W
-
Write “1” to assert a software reset to INTC block.
Reserved.
3-2
1
Reserved
RCIR
W
W
Write “1” to assert a software reset to CIR block.
Write “1” to assert a software reset to PWM block.
0
RPWM
Software Reset 2 Register ⎯ Offset 11h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
-
Reserved.
0: ACPI will reset by μC watchdog timeout.
3
2
1
0
ACPI_WD_RST_DIS R/W 5VSB
KBC_WD_RST_DIS R/W 5VSB
GPIO_WD_RST_DIS R/W 5VSB
CFG_WD_RST_DIS R/W 5VSB
1
1: ACPI won’t be reset by μC watchdog timeout.
0: KBC will reset by μC watchdog timeout.
1
1
1
1: KBC won’t be reset by μC watchdog timeout.
0: GPIO will reset by μC watchdog timeout.
1: GPIO won’t be reset by μC watchdog timeout.
0: CFG will reset by μC watchdog timeout.
1: CFG won’t be reset by μC watchdog timeout.
Software Reset 2 Register ⎯ Offset 11h
Bit
7-4
3
Name
Reserved
RACPI
RKBC
R/W Reset Default
Description
Reserved.
-
-
-
-
-
-
-
W
W
W
W
5VSB
5VSB
5VSB
5VSB
Write “1” to assert a software reset to ACPI block.
Write “1” to assert a software reset to KBC block.
Write “1” to assert a software reset to GPIO block.
Write “1” to assert a software reset to CFG block.
2
1
RGPIO
RCFG
0
211
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
