F81867
7.20.3
PWM Control μC Side Register (Base Address 0x1200, 256 bytes)
Clock Group 0 Divisor Register ⎯ Offset 00h
Bit
Name
R/W Reset Default
Description
7-0
GR0_DIV
R/W 5VSB 0x00 Clock group 0 divisor. The group 0 clock will be 12MHz/(GR0_DIV +1)*256.
Clock Group 1 Divisor Register ⎯ Offset 01h
Bit
Name
R/W Reset Default
Description
7-0
GR1_DIV
R/W 5VSB 0x00 Clock group 1 divisor. The group 2 clock will be 12MHz/(GR0_DIV +1)*256.
Clock Group 2 Divisor Register ⎯ Offset 02h
Bit
Name
R/W Reset Default
Description
7-0
GR2_DIV
R/W 5VSB 0x00 Clock group 2 divisor. The group 2 clock will be 12MHz/(GR0_DIV +1)*256.
Clock Group 3 Divisor Register ⎯ Offset 03h
Bit
Name
R/W Reset Default
Description
Clock group 3 divisor. The group 3 clock will be 12MHz/(GR0_DIV +1)*256.
The PWM clock source could be select among these four group clock.
7-0
GR3_DIV
R/W 5VSB
0x00
PWM Polarity Register ⎯ Offset 04h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
-
Reserved.
0: Normal PWM output.
3
2
1
0
PWM3_POL
PWM2_POL
PWM1_POL
PWM0_POL
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
1: PWM output is inverted.
0: Normal PWM output.
0
0
0
1: PWM output is inverted.
0: Normal PWM output.
1: PWM output is inverted.
0: Normal PWM output.
1: PWM output is inverted.
PWM Group Select Register ⎯ Offset 06h
Bit
Name
R/W Reset Default
Description
00: PWM3 clock source is group 0 clock.
01: PWM3 clock source is group 1 clock.
10: PWM3 clock source is group 2 clock.
11: PWM3 clock source is group 3 clock.
7-6
PCS3
R/W 5VSB
R/W 5VSB
00
00
00: PWM2 clock source is group 0 clock.
01: PWM2 clock source is group 1 clock.
10: PWM2 clock source is group 2 clock.
11: PWM2 clock source is group 3 clock.
5-4
PCS2
212
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
