F81867
0: μC and peripherals are reset by 5VSB power on reset, μC watchdog
timerout reset and Debug port exit reset.
0
EC_GRST
R/W 5VSB
0
1: μC and peripherals are reset by 5VSB power on reset and Debug port exit
reset.
WDT Reset Gate 1 Register ⎯ Offset 05h
Name R/W Reset Default
Bit
7
Description
0: SMFI will reset by μC watchdog timeout.
SMFI_WD_RST_DIS R/W 5VSB
Reserved
INTC_WD_RST_DIS R/W 5VSB
Reserved
1
-
1: SMFI won’t be reset by μC watchdog timeout.
6-5
4
-
-
Reserved.
0: INTC will reset by μC watchdog timeout.
1
-
1: INTC won’t be reset by μC watchdog timeout.
3-2
1
-
-
Reserved.
0: CIR will reset by μC watchdog timeout.
CIR_WD_RST_DIS R/W 5VSB
PWM_WD_RST_DIS R/W 5VSB
1
1: CIR won’t be reset by μC watchdog timeout.
0: PWM will reset by μC watchdog timeout.
0
1
1: PWM won’t be reset by C watchdog timeout.
WDT Reset Gate 2 Register ⎯ Offset 06h
Bit
Name
R/W
Default
Description
Reset
7-4
3
Reserved
-
-
Reserved.
-
0: ACPI will reset by μC watchdog timeout.
1: ACPI won’t be reset by μC watchdog timeout.
0: KBC will reset by μC watchdog timeout.
1: KBC won’t be reset by μC watchdog timeout.
0: GPIO will reset by μC watchdog timeout.
1: GPIO won’t be reset by μC watchdog timeout.
0: CFG will reset by μC watchdog timeout.
1: CFG won’t be reset by μC watchdog timeout
ACPI_WD_RST_DIS R/W
KBC_WD_RST_DIS R/W
GPIO_WD_RST_DIS R/W
CFG_WD_RST_DIS R/W
1
1
1
1
5VSB
5VSB
5VSB
5VSB
2
1
0
RTC RAM Write Protect Register ⎯ Offset 06h
Bit
Name
R/W
Default
Description
Set “1” to enable write protect for RTC RAM index
0xF0 ~ 0xFF.
Reset
7
RTC_WR_DIS_7
R/W
0
5VSB
Set “1” to enable write protect for RTC RAM index
0xE0 ~ 0xEF.
6
5
RTC_WR_DIS_6
RTC_WR_DIS_5
R/W
R/W
0
0
5VSB
5VSB
Set “1” to enable write protect for RTC RAM index
0xD0 ~ 0xDF.
210
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
