F81867
0: Rising edge of event will trigger an interrupt.
1: Falling edge of event will trigger an interrupt.
5
4
3
2
1
0
P80_INT_POL
H2E_INT_POL
ACPI_INT_POL
KBC_INT_POL
GPIO_INT_POL
HM_INT_POL
R/WC 5VSB
R/WC 5VSB
R/WC 5VSB
R/WC 5VSB
R/WC 5VSB
R/WC 5VSB
0
0
0
0
0
0
0: Rising edge of event will trigger an interrupt.
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
1: Falling edge of event will trigger an interrupt.
Interrupt Status 3 Register ⎯ Offset 10h
Bit
Name
R/W Reset Default
Description
Reserved.
7-2
Reserved
-
-
-
0: No power down event
1
0
PD_INT_ST
R/WC 5VSB
0
1: A power down event occurs. It is set by falling edge of PWROK. It is
cleared by read this bit.
0: No debug port event.
DBPORT_INT_ST R/WC 5VSB
0
1: A debug port interrupt event occurs. Clear by reading this bit.
Power Fail Register ⎯ Offset 11h
Bit
7-2
1
Name
Reserved
PWROK
R/W Reset Default
Description
-
-
-
Reserved.
R
5VSB
0
0
Status of PWROK.
0
PD_INT_EN
R/WC 5VSB
Set “1” to enable power fail interrupt.
7.20.2
General Control μC Side Register (Base Address 0x1100, 256 bytes)
Chip ID 1 Register ⎯ Offset 00h
Bit
Name
R/W Reset Default
Description
Description
Description
7-0
CHIPID1
R
-
0x00 Chip ID 1
Chip ID 2 Register ⎯ Offset 01h
Bit
Name
R/W Reset Default
7-0
CHIPID2
R
-
0x95 Chip ID 2
μC Reset Select Register ⎯ Offset 04h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
-
Reserved.
209
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
