M12L16161A
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C L O C K
C KE
H I G H
CS
RAS
CAS
A D D R
C Aa
R Aa
C Ab
B A
R Aa
A1 0 / AP
*Note2
Q A a 2 Q A a 3 Q A a 4
1
1
Q A a 1
Q A b 3 Q A b 4 Q A b 5
Q A b 0
Q A b 1 Q A b 2
Q A a 0
C L= 2
D Q
2
2
Q A a 2 Q A a 3 Q A a 4
Q A b 1
Q A b 0
Q A b 5
Q A a 0
Q A b 3
Q A b 4
Q A a 1
Q A b 2
C L= 3
WE
*N o t e 1
D Q M
R e a d
B u r s t S t o p
R e a d
P r e c h a r g e
(A- B a n k )
R o w Ac t i v e
(A- B a n k )
(A- B a n k )
(A- B a n k )
: D o n ' t C a r e
1.Burst can’t end in full page mode, so auto precharge can’t issue.
*Note:
2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.21
:
Revis ion 1.3u
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
