M12L16161A
Burst Read Single bit Write Cycle @Burst Length=2
1 6
1 7
1 8
0
1
2
5
9
1 0
1 1
1 2
1 3
1 4
1 5
1 9
3
4
6
7
8
C L O C K
* N o t e 1
H IG H
C K E
C S
R A S
C A S
* N o t e 2
R A a
R B b
C A a
R A c
C B c
C A b
C A d
A D D R
B A
R B b
A 1 0 / A P
R A a
R A c
D A a 0
D A a 0
Q A d 0
Q A b 0 Q A b 1
Q A d 1
C L = 2
D B c 0
D B c 0
D Q
C L = 3
Q A b 1
Q A d 0 Q A d 1
Q A b 0
W E
D Q M
R o w A c t i v e
( A - B a n k )
R o w A c t i v e
( A - B a n k )
R e a d
( A - B a n k )
Row Active
(B-Ba n k )
P r e c h a r g e
( A - B a n k )
W r i t e w i t h
Rea d with
W r i t e
( A - B a n k )
A u t o P r e c h a r g e
( B - B a n k )
Au to Prech arge
(A-Ban k )
: D o n ' t C a r e
*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.When BRSW write command with auto precharge is executed, keep it in mind that RAS should not be violated.
t
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.23
:
Revis ion 1.3u
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
