M12L16161A
Read & Write Cycle with auto Precharge @ Burst Length =4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H IG H
C K E
C S
R A S
C A S
A D D R
C b
R b
R a
C a
B A
A 1 0 / A P
R a
R b
Q a 2
C L = 2
DQ
Q a 0 Q a 1
Q a 3
Q a 2
D b 0 D b 1
D b 2 D b 3
C L = 3
Q a 3
D b 3
D b 0 D b 1 D b 2
Q a 0 Q a 1
W E
D Q M
Row Active
Rea d with
CL= 2
W r i t e w i t h
A u t o P r e c h a r g e
( B - B a n k )
A u t o P r e c h a r g e
S t a r t P o i n t
( B - B a n k )
(
A - Ba n k )
Au to Prech a rge
( A - Ban k )
Au to Prech a rge
Start Poin t
( A - Ba n k)
Row Active
( B - Ban k )
CL= 3
Au to Prech arge
Start Poin t
( A - Ban k )
: D o n ' t C a r e
*Note: 1. CDL Should be controlled to meet minimum RAS before internal precharge start
t
t
(In the case of Burst Length=1 & 2 and BRSW mode)
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.19
:
Revis ion 1.3u
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
