M12L16161A
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
1 6
1 7
1 8
1 1
1 2
1 3
1 4
1 5
1 9
0
1
2
5
9
1 0
3
4
6
7
8
C L O C K
C K E
C S
R A S
C A S
C a
R a
C b
C c
A D D R
B A
A 1 0 / A P
D Q
R a
Q a 0 Q a 1
Q a 3
t S
D c 0
D c 2
Q a 2
Q b 0 Q b 1
t S H
H Z
Z
W E
* N o t e 1
D Q M
C l o c k
W r i t e
D Q M
R o w A c t i v e
R e a d
R e a d
W r i t e
D Q M
S u s p e n s i o n
C l o c k
S u s p e n s i o n
R e a d D Q M
W r i t e
: D o n ' t C a r e
*Note:1.DQM is needed to prevent bus contention.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.20
:
Revis ion 1.3u