M12L16161A
Page Write Cycle at Different Bank @Burst Length = 4
10
1 1
1
2
3
5
6
9
13
16
17
0
4
8
15
18
19
12
7
14
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note2
ADDR
BA
RAa
CAa
CBb
CBd
RBb
CAc
RAa
RBb
A10/ AP
DQ
DAa1 DAa2
DBb0
DBd1
DAa0
DAa3
DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
tCDL
tRDL
WE
*Note1
DQM
Prech arge
Row Active
(A-Bank)
Write
Row Active
(B-Ba n k)
Write
Write
(A-Bank)
Write
(Both Banks )
(B-Ban k)
(A-Bank)
(B-Ban k)
: Don 't care
*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.17
:
Revis ion 1.3u
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
