M12L16161A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1 8
1
5
1
6
1
7
1 9
CLOCK
CKE
HIGH
C S
R A S
CAS
RAc
ADDR
CAa
CBb
CAc
RAa
RBb
BA
RBb
RBb
RAa
RAc
A10/AP
CL=2
*Note1
tCDL
QAa1 QAa2 QAa3
DBb1 DBb2
QAa0
DBb0
DBb3
QAc0 QAc1
QAc2
DQ
QAa1
CL=3
WE
QAa0
QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
DQM
Write
(B-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note: 1. CDL should be met to complete write.
t
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.18
:
Revis ion 1.3u