M12L16161A
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
1 6
1 7
1 8
1 1
1 2
1 3
1 4
1 5
1 9
0
1
2
5
9
1 0
3
4
6
7
8
C L O C K
* N o t e 2
t S S
t S S
* N o t e 1
t S S
C K E
C S
* N o t e 3
R A S
C A S
R a
C a
A D D R
B A
R a
A 1 0 / A P
t S H Z
Q a 1
Q a 0
Q a 2
D Q
W E
D Q M
Row Active
Read
P r e c h a r g e
P r e c h a r g e
P o w e r - D o w n
E n t r y
Active
Prech a rge
Power-Down
Exit
Active
Power-down
En try
Power-down
Exit
:
D o n ' t c a r e
1.Both banks should be in idle state prior to entering precharge power down mode.
2.CKE should be set high at least 1CLK+tss prior to Row active command.
3.Can not violate minimum refresh specification. (32ms)
*Note :
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.24
:
Revis ion 1.3u
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
