M12L16161A
Page Read Cycle at Different Bank @ Burst Length=4
5
6
9
15
1 6
0
1
3
4
12
7
2
8
10
11
13
19
1 4
17
18
CLOCK
CKE
HIGH
*Note1
CS
RAS
*Note2
CAS
ADDR
BA
RAa
CAa
CAc
CBd
CAe
RBb
CBb
RAa
RBb
A10/ AP
CL=2
QAa 0 QAa 1 QAa2 QAa3 QBb 0 QBb1 QBb 2 QBb3 QAc0 QAc1 QBd 0 QBd1 QAe0 QAe1
D Q
CL=3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb 1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
WE
DQM
Rea d
Rea d
Rea d
Row Active
(A-Bank)
Prech arge
(A-Ba n k)
Rea d
Read
(B-Ban k)
(A-Ba nk)
(B-Ban k)
(A-Ba nk )
(A-Bank)
Row Active
(B-Ban k)
: Don 't care
*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
:
Publication Da te J an. 2000
Elite Semiconductor Memory Technology Inc.
P.16
:
Revis ion 1.3u
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
