Page 72
Epson Research and Development
Vancouver Design Center
7.3.2 EDO-DRAM CAS Before RAS Refresh Timing
t1
Memory
Clock
t2
t3
RAS#
t4
t5
t6
CAS#
Figure 7-14: EDO-DRAM CAS Before RAS Refresh Timing
Table 7-15: EDO-DRAM CAS Before RAS Refresh Timing
Symbol
Parameter
Min
25
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
Memory clock period
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
2 t1
t2
RAS# precharge time (REG[02Ah] bits 1-0 = 01)
1.45 t1
t1
RAS# precharge time (REG[02Ah] bits 1-0 = 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 01)
RAS# pulse width (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 01)
RAS# pulse width (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 01)
RAS# pulse width (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 10)
CAS# precharge time (REG[02Ah] bits 1-0 = 00)
3 t1 - 7
3.45 t1 - 1
4 t1 - 7
2 t1 - 7
2.45 t1 - 1
3 t1 - 7
t1 - 7
t3
1.45 t1 - 1
2 t1 - 7
2 t1
t4
t5
CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
t1
0.45 t1
CAS# setup time (REG[02Ah] bits 1-0 = 00 or 10)
t1 - 4
2.45 t1 - 4
3 t1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS# setup time (REG[02Ah] bits 1-0 = 01)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 01)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 10)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 01)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 10)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 01)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 10)
3.45 t1 - 4
1.45 t1 - 4
2 t1
t6
2.45 t1 - 4
0.45 t1 - 4
t1
1.45 t1 - 4
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
