Epson Research and Development
Page 75
Vancouver Design Center
Table 7-17: FPM-DRAM Read, Write, Read-Write Timing
Symbol
Parameter
Min
40
Max
Units
ns
t1
Memory clock
Random read or write cycle time (REG[02Bh] bits 1-0 = 00)
Random read or write cycle time (REG[02Bh] bits 1-0 = 01)
Random read or write cycle time (REG[02Bh] bits 1-0 = 10)
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
5 t1
4 t1
3 t1
2 t1
1.45 t1
t1
ns
t2
t3
ns
ns
ns
RAS# precharge time (REG[02Ah] bits 1-0 = 01)
ns
RAS# precharge time (REG[02Ah] bits 1-0 = 10)
ns
RAS# to CAS# delay time (REG[02Ah] bit 4 = 0 and bits 1-0
= 00 or 10)
2.45 t1 - 3
1.45 t1 - 3
2 t1 - 3
2.55 t1
1.55 t1
2 t1
ns
ns
ns
ns
RAS# to CAS# delay time (REG[02Ah] bit 4 = 1 and bits 1-0
= 00 or 10)
t4
RAS# to CAS# delay time (REG[02Ah] bit 4 = 0 and bits 1-0
= 01)
RAS# to CAS# delay time (REG[02Ah] bit 4 = 1 and bits 1-0
= 01)
t1 - 3
t1
t5
t6
t7
CAS# precharge time
0.45 t1
0.45 t1 - 1
0.45 t1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS# pulse width
RAS# hold time
Row address setup time (REG[02Ah] bits 1-0 = 00
Row address setup time (REG[02Ah] bits 1-0 = 01)
Row address setup time (REG[02Ah] bits 1-0 = 10)
Row address hold time (REG[02Ah] bits 1-0 = 00 or 10)
Row address hold time (REG[02Ah] bits 1-0 = 01)
Column address set-up time
2 t1 - 2
t8
1.45 t1 - 2
t1 - 2
t1 - 3
t9
0.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 1
t10
t11
Column address hold time
Read Command setup (REG[02Ah] bit 4 = 0 and bits 1-0 =
00)
4.45 t1 - 1
ns
t12
t13
Read Command setup (REG[02Ah] bit 4 = 1 and bits 1-0 =
01 or 10)
2.45 t1 - 1
3.45 t1 - 1
4 t1 - 1
ns
ns
ns
Read Command setup (all other REG[02Ah] values)
Read Command hold (REG[02Ah] bit 4 = 0 and bits 1-0 =
00)
Read Command hold (REG[02Ah] bit 4 = 1 and bits 1-0 = 01
or 10)
2 t1 - 1
3 t1 - 1
ns
ns
Read Command hold (all other REG[02Ah] values)
Read data setup referenced from CAS#
Read Data turn-off from CAS#
Write command setup time
t14
t15
t16
t17
t18
3
3
ns
ns
0.45 t1 - 1
0.45 t1 - 1
0.45 t1 - 4
ns
ns
ns
Write command hold time
Write Data setup time
t19
t20
t21
Write Data hold time
0.45 t1
0.45 t1
0.45 t1
ns
ns
ns
MD tri-state
0.55 t1 + 19
CAS# to WE# active during read-write cycle
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
