Epson Research and Development
Page 73
Vancouver Design Center
7.3.3 EDO-DRAM Self-Refresh Timing
MCLK can be stopped
(See Note)
t1
Memory
Clock
t2
RAS#
CAS#
t3
t5
t4
Figure 7-15: EDO - DRAM Self-Refresh Timing
Note
MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.
Table 7-16: EDO - DRAM Self-Refresh Timing
Symbol
Parameter
Min
25
Max
Units
ns
t1
Memory clock period
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# precharge time (REG[02Ah] bits 1-0 = 01)
RAS# precharge time (REG[02Ah] bits 1-0 = 10)
RAS# to CAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# to CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
CAS# precharge time (REG[02Ah] bits 1-0 = 00)
CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
2 t1
ns
t2
1.45 t1
t1
ns
ns
1.45 t1
0.45 t1
2 t1
ns
t3
t4
ns
ns
t1
ns
0.45 t1
ns
CAS# setup time (REG[02Ah] bits 1-0 = 00 or 10)
CAS# setup time (REG[02Ah] bits 1-0 = 01)
t5
t1 - 4
ns
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
