Page 68
Epson Research and Development
Vancouver Design Center
7.2 Clock Timing
7.2.1 Input Clocks
t
t
PWH
PWL
90%
V
IH
V
IL
10%
t
t
r
f
T
OSC
Figure 7-11: CLKI Clock Input Requirements
Table 7-11: Clock Input Requirements for CLKI/CLKI2/BUSCLK divided down internally
Symbol
fOSC
TOSC
tPWH
tPWL
tf
Parameter
Input Clock Frequency
Min
Max
Units
MHz
ns
80
Input Clock Period
1/fOSC
5.6
Input Clock Pulse Width High
Input Clock Pulse Width Low
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
ns
5.6
ns
5
5
ns
tr
ns
1
Table 7-12: Clock Input Requirements for CLKI or BUSCLK if used directly for MCLK
Symbol
fOSC
TOSC
tPWH
tPWL
tf
Parameter
Input Clock Frequency
Min
Max
Units
MHz
ns
40
Input Clock Period
1/fOSC
11.31
11.31
Input Clock Pulse Width High
Input Clock Pulse Width Low
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
ns
ns
5
5
ns
tr
ns
Note
1. MCLK must have a duty cycle of 50% ± 5%.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
