Epson Research and Development
Page 69
Vancouver Design Center
7.2.2 Internal Clocks
Table 7-13: Internal Clock Requirements
Symbol
fMCLK
Parameter
Min
0
Max
40
Units
Memory Clock Frequency
LCD Pixel Clock Frequency
CRT/TV Pixel Clock Frequency
MediaPlug Clock Frequency
MHz
MHz
MHz
MHz
fLCD PCLK
0
40
fCRT/TV PCLK
fMediaPlug Clock
0
Note 1
10
0
1. The maximum CRT pixel clock is 40MHz.
The TV pixel clock for NTSC output is fixed at 14.318MHz.
The TV pixel clock for PAL output is fixed at 17.734MHz.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10