Epson Research and Development
Page 49
Vancouver Design Center
Table 7-1: Generic Timing
3.0V
5.0V
Symbol
Parameter
Min
Max
Min
Max Units
fCLK
TCLK
t2
Clock frequency
50
50
MHz
ns
Clock period
1/fCLK
1/fCLK
Clock pulse width high
Clock pulse width low
6
6
6
6
ns
t3
ns
A[20:1], M/R# setup to first CLK where CS# = 0 and either RD0#,
RD1#= 0 or WE0#, WE1#= 0
t4
t5
4
0
3
0
ns
ns
A[20:1], M/R# hold from rising edge of either RD0#, RD1# or WE0#,
WE1#
t6
t7
t8
CS# hold from rising edge of either RD0#, RD1# or WE0#, WE1#
Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# driven low
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# tri-state
0
4
3
0
3
2
ns
ns
ns
21
14
13
7
D[15:0] setup to third CLK where CS# = 0 and WE0#, WE1# = 0 (write
cycle)
t9
0
0
ns
t10
t11
t12
t13
D[15:0] hold (write cycle)
0
3
0
7
0
3
0
4
ns
ns
ns
ns
Falling edge RD0#, RD1# to D[15:0] driven (read cycle)
D[15:0] setup to rising edge WAIT# (read cycle)
Rising edge of RD0#, RD1# to D[15:0] tri-state (read cycle)
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15
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
