Page 50
Epson Research and Development
Vancouver Design Center
7.1.2 Hitachi SH-4 Interface Timing
TCKIO
t2
t3
CKIO
t4
t5
A[20:1], M/R#
RD/WR#
t6
t7
BS#
t17
t8
t12
CSn#
t10
t9
WEn#
RD#
t18
t12
t11
RDY#
t14
t13
D[15:0](write)
t15
t16
D[15:0](read)
Figure 7-2: Hitachi SH-4 Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
Note
The SH-4 Wait State Control Register for the area in which the S1D13506 resides must
be set to a non-zero value. The SH-4 read-to-write idle cycle transition must be set to a
non-zero value (with reference to BUSCLK).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
