Page 130
Epson Research and Development
Vancouver Design Center
bits 5-4
CRT/TV PCLK Divide Select Bits[1:0]
These bits determine the divide used to generate the CRT/TV pixel clock from the
CRT/TV pixel clock source.
Table 8-6: CRT/TV PCLK Divide Selection
CRT/TV PCLK Source to CRT/TV PCLK
CRT/TV PCLK Divide Select Bits
Frequency Ratio
00
01
10
11
1:1
2:1
3:1
4:1
bits 1-0
CRT/TV PCLK Source Select Bits [1:0]
These bits determine the source of the CRT/TV pixel clock for the CRT/TV
display.
Table 8-7: CRT/TV PCLK Source Selection
CRT/TV PCLK Source Select Bits
CRT/TV PCLK Source
CLKI
00
01
10
11
BUSCLK
CLKI2
MCLK (see note)
Note
MCLK may be a previously divided down version of CLKI, CLKI2 or BUSCLK.
MediaPlug Clock Configuration Register
REG[01Ch]
RW
MediaPlug
MediaPlug
MediaPlug
MediaPlug
n/a
n/a
Clock Divide Clock Divide
Select Bit 1 Select Bit 0
n/a
n/a
Clock Source Clock Source
Select Bit 1 Select Bit 0
bits 5-4
MediaPlug Clock Divide Select Bits[1:0]
These bits determine the divide used to generate the MediaPlug Clock from the CRT/TV
pixel clock source.
Table 8-8: MediaPlug Clock Divide Selection
MediaPlug Clock Source to CRT/TV Pixel
MediaPlug Clock Divide Select Bits
Clock Frequency Ratio
00
01
10
11
1:1
2:1
3:1
4:1
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
