Epson Research and Development
Page 127
Vancouver Design Center
General IO Pins Control Register
REG[008h]
RW
GPIO3 Pin
IO Status
GPIO2 Pin
IO Status
GPIO1 Pin
IO Status
Reserved
Reserved
Reserved
Reserved
Reserved
bit 3
GPIO3 Pin IO Status
When GPIO3 is configured as an output, writing a 1 to this bit drives GPIO3 high and
writing a 0 to this bit drives GPIO3 low.
When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3.
Note
Note that MD[7:6] must be properly configured at the rising edge of RESET# to enable
GPIO3, otherwise GPIO3 will be used as MA9 for the DRAM and this bit will have no
hardware effect. (See Table 8-2: “MA[11:9]/GPIO[1:3] Pin Functionality”).
bit 2
GPIO2 Pin IO Status
When GPIO2 is configured as an output, writing a 1 to this bit drives GPIO2 high and
writing a 0 to this bit drives GPIO2 low.
When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2.
Note
Note that MD[14] and MD[7:6] must be properly configured at the rising edge of RE-
SET# to enable GPIO2, otherwise GPIO2 will be used as MA11 for the DRAM or as the
MediaPlug VMPEPWR output and this bit will have no hardware effect. (See Table 8-2:
“MA[11:9]/GPIO[1:3] Pin Functionality”).
bit 1
GPIO1 Pin IO Status
When GPIO1 is configured as an output, writing a 1 to this bit drives GPIO1 high and
writing a 0 to this bit drives GPIO1 low.
When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1.
Note
Note that MD[7:6] must be properly configured at the rising edge of RESET# to enable
GPIO1, otherwise GPIO1 will be used as MA10 for the DRAM and this bit will have no
hardware effect. (See Table 8-2: “MA[11:9]/GPIO[1:3] Pin Functionality”).
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
