DM9016
3-port switch with Processor Interface
6.29 Processor Data Bus Driving Capability Register (38H)
Bit
Name
Default
Description
RESERVED
0,RW
Reserved
7
SD Bus Current Driving/Sinking Capability
00: 2mA
6:5
ISA_CURR
P01,RW 01: 4mA (default)
10: 6mA
11: 8mA
4:3
2
Reserved
STEP
P0,RW
P0,RW
Reserved
Data Bus Output stepping
1: disabled
0: enabled
Eliminate IOW spike
0: Disable
1: Eliminate about 2ns IOW spike
Eliminate IOR spike
0: Disable
1
0
IOW_SPIKE
IOR_SPIKE
P0,RW
P1,RW
1: Eliminate about 2ns IOR spike
6.30 IRQ Pin Control Register (39H)
Bit
Name
Default
Description
IRQ Delayed Output Interval
7:5
IRQ_DELAY
PS0,RW
This field determines the IRQ delayed output interval in multiples of 40
milliseconds(ms)
IRQ Pin Output Type Control
1: IRQ open-collector output
0: IRQ direct output
1
0
IRQ_TYPE
IRQ_POL
PET0,RW
PET0,RW
IRQ Pin Polarity Control
1: IRQ active low
0: IRQ active high
6.31 Port 2 Driving Capability Register (3AH)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
Port 2 TXD/TXE Current Driving/Sinking Capability
6:5
4:0
00: 2mA
01: 4mA (default)
10: 6mA
P2_CURR
P01,RW
0,RW
11: 8mA
RESERVED
Reserved
6.32 RX Control Register 2 (3CH)
Bit
7:2
1
Name
Reserved
DIS_BCAST
Default
PS0,RO
PH0,RW
Description
Reserved
Abort broadcast packet if its size > 256 bytes
Jump to Next Start of Receiving Packet
Write 1 to launch and clear automatically after 10ns.
0
NEXT_RX
PH0,RW
28
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
