DM9016
3-port switch with Processor Interface
59H:
Bit
7:0
Name
DSP_CTL2
Default
Description
PH0,RW DSP Control Register 2 for testing only (register 59H)
6.44 Per Port Control/Status Index Register (60H)
Bit
7:5
4:2
1:0
Name
Default
Description
RESERVED PHS0,RW Reserved
RESERVED
INDEX
0,RO
PHS0,RW Port index for register 61h~84h
Write the port number to this register before write/read register 61h~84h.
Reserved
6.45 Per Port Control Data Register (61H)
Bit
7
6
Name
FAST_LEV
PARTI_EN
Default
Description
PHE0,RW IGMP Snooping Fast Leave Enable
PHE0,RW Enable Partition Detection
5
NO_DIS_RX PHE0,RW Don’t Discard RX Packets when Ingress Bandwidth Control
When received packets bandwidth reach Ingress bandwidth threshold,
the packets over the threshold are not discarded but with flow control.
4
FLOW_DIS
PHE0,RW Flow control in full duplex mode, or back pressure in half duplex mode
enable
0: enable
1: disable
3
2
1
0
BANDWIDTH PHE0,RW Bandwidth Control
0: Control with Ingress and Egress separately, ref to Register 66H.
1: Control with Ingress or Egress, ref to Register 67H
PHE0,RW Broadcast packet filter
BP_DIS
0: accept broadcast packets
1: reject broadcast packets
MP_DIS
PHE0,RW Multicast packet filter
0: accept multicast packets
1: reject multicast packets
MP_STORM
PE0,RW Broadcast Storm Control
0: only broadcast packets storm are controlled
1: multicast packets also same as broadcast storm control.
Preliminarydatasheet
DM9016-13-DS-P01
March 26, 2009
31
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
