DM9016
3-port switch with Processor Interface
6.46 Per Port Status Data Register (62H)
Bit
7:6
5
Name
RESERVED
LP_FCS
BIST
Default
P0,RO
P0,RO
P0,RO
Description
Reserved
Link Partner Flow Control Enable Status
BIST status
4
0: SRAM BIST pass
1: SRAM BIST fail
Reserved
3
2
RESERVED
SPEED2
0,RO
P0,RO
Speed Status
0: 10Mbps, 1:100Mbps
Duplex Status
0: half-duplex, 1: full-duplex
Link Status
1
0
FDX2
LINK2
P0,RO
P0,RO
0: not Link status, 1: Link status
6.47 Per Port Forward Control Register (65H)
Bit
7
6
5
4
3
2
1
0
Name
LOOPBACK
MONI_TX
MONI_RX
DIS_BMP
RESERVED
TX_DIS
Default
Description
PHE0,RW Loop-back Mode
PHE0,RW TX Packet Monitored
PHE0,RW RX Packet Monitored
PHE0,RW Broad/Multicast packet do not monitored
PH0,RW Reserved
PHE0,RW Packet Transmit Disabled
PHE0,RW Packet Receive Disabled
PHE0,RW Address Learning Disabled
RX_DIS
ADR_DIS
32
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
