DM9016
3-port switch with Processor Interface
6.38 Switch Control Register (52H)
Bit
Name
Default
Description
7
MEM_BIST
PH0,RO
Address Memory Test BIST Status
0: OK
1: Fail
6
5
RST_SW
P0,RW
P0,RW
Reset Switch Core
Write 1 to launch and clear automatically after 10us.
Reset Analog PHY Core
RST_ANLG
Write 1 to launch and clear automatically after 10us.
4:3
2
1:0
SNF_PORT PHE00,RW Sniffer Port Number
CRC_DIS
PHE0,RW Switch CRC Checking Disable
0,RO Reserved
RESERVED
6.39 VLAN Control Register (53H)
Bit
7
Name
TOS6
Default
PHE0,RW Full ToS Using Enable
0: check most significant 3-bit only of TOS
Description
1: check most significant 6-bit of TOS
Reserved
PHE0,RW Unicast Packet Can Across VLAN Boundary
PHE0,RW Replace VID FFF
PHE0,RW Replace VID 001
PHE0,RW Replace VID 000
PHE0,RW Replace Priority Field in The Tag
PHE0,RW VLAN Mode Enable
0: port-base VLAN
6
5
4
3
2
1
0
RESERVED
UNICAST
VIDFFF
VID1
0,RO
VID0
PRI
VLAN
1: 802.1Q base VLAN mode enable
6.41 Bandwidth LED Control Register (55H)
Bit
7,6
5
4
3
2
1
0
Name
Default
Description
RESERVED PH0,RW Reserved
P2_TX
P2_RX
P1_TX
P1_RX
P0_TX
P0_RX
PH1,RW Port 2 transmit as event of bandwidth LED source
PH0,RW Port 2 receive as event of bandwidth LED source
PH1,RW Port 1 transmit as event of bandwidth LED source
PH0,RW Port 1 receive as event of bandwidth LED source
PH1,RW Port 0 transmit as event of bandwidth LED source
PH0,RW Port 0 receive as event of bandwidth LED source
6.42 STP Control Register (56H)
Bit
7:1
0
Name
RESERVED
STPEN
Default
0,RO
Description
Reserved
PS0,RW Spanning Tree Protocol Enabled
6.43 DSP PHY Control Register (58H~59H)
58H:
Bit
Name
Default
Description
7:0
DSP_CTL1
PH0,RW DSP Control Register 1 for testing only (register 58H)
30
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
