DM9016
3-port switch with Processor Interface
6.5 RX Status Register (06H)
Bit
7
6
Name
RESERVED
MF
Default
0,RO
0,RO
0,RO
Description
Reserved
Multicast Frame
Received Frame Type
00: Reserved
5:4
PKT_TYPE
01: IGMP packet
10: MLD packet
11: BPDU packet
Source Port Number
CRC Error
3:2
1
0
SRCP
CE
FOE
0,RO
0,RO
0,RO
FIFO Overflow Error
6.6 Receive Overflow Counter Register (07H)
Bit
7
Name
RXFU
Default
PHS0,R/C Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
PHS0,R/C Receive Overflow Counter
Description
6:0
ROC
This is a statistic counter to indicate the received packet count upon FIFO overflow
6.7 Flow Control Register (0AH)
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
RX Flow Control Enable
Enables the pause packet for high/low water threshold control
Reserved
5
FLOW_EN PHS0,RW
RESERVED 0,RO
4:0
6.8 EEPROM & PHY Control Register (0BH)
Bit
7
6
Name
RESERVED
EETYPE
Default
0,RO
0,RO
Description
Reserved
EEPROM Type
0: 93C46
1: 93C56
5
REEP
PH0,RW Reload EEPROM.
Note: Driver needs to clear it up after the operation completes
PH0,RW Write EEPROM Enable
PH0,RW EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
4
3
WEP
EPOS
2
1
0
ERPRR
ERPRW
ERRE
PH0,RW EEPROM Read or PHY Register Read Command.
Note:: Driver needs to clear it up after the operation completes.
PH0,RW EEPROM Write or PHY Register Write Command.
Note:: Driver needs to clear it up after the operation completes.
PH0,RO EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
24
Preliminary datasheet
DM9016-13-DS-P01
March 26, 2009
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
