PSoC® 3: CY8C32 Family
Data Sheet
Figure 11-53. Synchronous Read Cycle Timing
Tcp/2
EM_Clock
EM_CEn
Tceld
Taddrv
Toeld
Tcehd
Taddriv
EM_Addr
EM_OEn
Address
Toehd
Tds
Data
EM_Data
Tadschd
Tadscld
EM_ ADSCn
Table 11-54. Synchronous Read Cycle Specifications
Parameter
T
Description
EMIF clock period[44]
Conditions
Vdda ≥ 3.3 V
Min
30.3
T/2
Typ
–
Max
–
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Tcp/2
EM_Clock pulse high
–
–
Tceld
EM_CEn low to EM_Clock high
EM_Clock high to EM_CEn high
EM_Addr valid to EM_Clock high
EM_Clock high to EM_Addr invalid
EM_OEn low to EM_Clock high
EM_Clock high to EM_OEn high
Data valid before EM_OEn high
EM_ADSCn low to EM_Clock high
EM_Clock high to EM_ADSCn high
5
–
–
Tcehd
Taddrv
Taddriv
Toeld
T/2 – 5
5
–
–
–
–
T/2 – 5
5
–
–
–
–
Toehd
Tds
T
–
–
T + 15
5
–
–
Tadscld
Tadschd
–
–
T/2 – 5
–
–
Note
44. Limited by GPIO output frequency, see Table 11-10 on page 72.
Document Number: 001-56955 Rev. *J
Page 98 of 119
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