PSoC® 3: CY8C32 Family
Data Sheet
Figure 11-54. Synchronous Write Cycle Timing
Tcp/2
EM_Clock
EM_CEn
Tceld
Taddrv
Tweld
Tds
Tcehd
Taddriv
EM_Addr
Address
Twehd
EM_WEn
EM_Data
Tdh
Data
Tadschd
Tadscld
EM_ ADSCn
Table 11-55. Synchronous Write Cycle Specifications
Parameter
T
Description
EMIF clock Period[45]
Conditions
Min
Typ
–
Max
–
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Vdda ≥ 3.3 V
30.3
Tcp/2
EM_Clock pulse high
T/2
–
–
Tceld
EM_CEn low to EM_Clock high
EM_Clock high to EM_CEn high
EM_Addr valid to EM_Clock high
EM_Clock high to EM_Addr invalid
EM_WEn low to EM_Clock high
EM_Clock high to EM_WEn high
Data valid before EM_Clock high
Data invalid after EM_Clock high
EM_ADSCn low to EM_Clock high
EM_Clock high to EM_ADSCn high
5
–
–
Tcehd
Taddrv
Taddriv
Tweld
Twehd
Tds
T/2 – 5
–
–
5
–
–
T/2 – 5
–
–
5
–
–
T/2 – 5
–
–
5
–
–
Tdh
T
5
–
–
Tadscld
Tadschd
–
–
T/2 – 5
–
–
Note
45. Limited by GPIO output frequency, see Table 11-10 on page 72.
Document Number: 001-56955 Rev. *J
Page 99 of 119
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