PSoC® 3: CY8C32 Family
Data Sheet
11.4.5 External Memory Interface
EM_CEn
Figure 11-51. Asynchronous Read Cycle Timing
Tcel
Taddrv
Taddrh
EM_Addr
Address
Toel
EM_OEn
EM_WEn
EM_Data
Tdoesu
Tdoeh
Data
Table 11-52. Asynchronous Read Cycle Specifications
Parameter
T
Description
EMIF clock period[42]
Conditions
Vdda ≥ 3.3 V
Min
30.3
2T – 5
–
Typ
Max
Units
nS
–
–
–
–
–
–
–
–
Tcel
EM_CEn low time
2T+ 5
nS
Taddrv
Taddrh
Toel
EM_CEn low to EM_Addr valid
Address hold time after EM_Wen high
EM_OEn low time
5
nS
T
–
nS
2T – 5
T + 15
3
2T + 5
nS
Tdoesu
Tdoeh
Data to EM_OEn high setup time
Data hold time after EM_OEn high
–
–
nS
nS
Note
42. Limited by GPIO output frequency, see Table 11-10 on page 72.
Document Number: 001-56955 Rev. *J
Page 96 of 119
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