PSoC® 3: CY8C32 Family
Data Sheet
Figure 2-3. 68-pin QFN Part Pinout[10]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
P0[3] (GPIO, Extref0)
51
1
2
3
4
5
6
50
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
49
48
47
Lines show Vddio
to I/O supply
association
(I2C0: SDA, SIO) P12[5]
Vssb
Ind
P12[3] (SIO)
P12[2] (SIO)
Vssd
46
45
Vboost
Vbat
7
8
9
Vdda
Vssa
44
43
QFN
(Top View)
Vssd
Vcca
10
42
41
XRES
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(configurable XRES, GPIO) P1[2]
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
11
12
13
40
39
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
(TDO, SWV, GPIO) P1[3] 14
38
37
36
35
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
Vddio1
15
16
17
P3[7] (GPIO)
P3[6] (GPIO)
Vddio3
Notes
9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
10. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
Document Number: 001-56955 Rev. *J
Page 7 of 119
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