PSoC® 3: CY8C32 Family
Data Sheet
Figure 6-9. SIO Input/Output Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Buffer
Thresholds
Reference Level
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Pin Interrupt Signal
PICU[x]INTSTAT
Input Buffer Disable
Interrupt
Logic
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
Driver
Vhigh
PRT[x]SYNC_OUT
PRT[x]DR
0
1
In
Digital System Output
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Slew
Cntl
PIN
Bidirectional Control
PRT[x]BIE
OE
Figure 6-10. USBIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
USB Receiver Circuitry
PRT[x]DBL_SYNC_IN
USBIO_CR1[0,1]
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Pin Interrupt Signal
PICU[x]INTSTAT
Interrupt
Logic
Digital Output Path
PRT[x]SYNC_OUT
USBIO_CR1[7]
D+ pin only
Vddd Vddd
USB or I/O
Vddd
USB SIE Control for USB Mode
Vddd
USBIO_CR1[4,5]
Digital System Output
PRT[x]BYP
0
1
In
Drive
Logic
5 k
1.5 k
PIN
USBIO_CR1[2]
USBIO_CR1[3]
USBIO_CR1[6]
D+ 1.5 k
D+D- 5 k
Open Drain
Document Number: 001-56955 Rev. *J
Page 36 of 119
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