CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.6
Slave FIFO Synchronous Read
tIFCLK
IFCLK
SLRD
tRDH
tSRD
tXFLG
FLAGS
DATA
N+1
tXFD
N
tOEon
tOEoff
SLOE
[19]
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram
[21]
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
20.83
18.7
0
Max.
Unit
ns
t
t
t
t
t
t
t
IFCLK Period
IFCLK
SLRD to Clock Set-up Time
ns
SRD
Clock to SLRD Hold Time
ns
RDH
OEon
OEoff
XFLG
XFD
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
10.5
10.5
9.5
ns
ns
ns
TBD
11
ns
[21]
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Parameter
Description
Min.
20.83
12.7
3.7
Max.
Unit
ns
t
t
t
t
t
t
t
IFCLK Period
200
IFCLK
SLRD to Clock Set-up Time
ns
SRD
Clock to SLRD Hold Time
ns
RDH
OEon
OEoff
XFLG
XFD
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
10.5
10.5
13.5
15
ns
ns
ns
TBD
ns
Document #: 38-08032 Rev. *G
Page 40 of 55
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