CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.5
GPIF Synchronous Signals
tIFCLK
IFCLK
tSGA
GPIFADR[8:0]
RDYX
tSRY
tRYH
valid
DATA(input)
tSGD
tDAH
CTLX
tXCTL
DATA(output)
N
N+1
tXGD
[19]
Figure 9-4. GPIF Synchronous Signals Timing Diagram
[20, 21]
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
20.83
8.9
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
IFCLK Period
RDY to Clock Set-up Time
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
X
Clock to RDY
X
GPIF Data to Clock Set-up Time
GPIF Data Hold Time
9.2
0
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
7.5
11
Clock to CTL Output Propagation Delay
6.7
X
[21]
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Parameter
Description
Min.
20.83
2.9
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
[22]
t
t
t
t
t
t
t
t
IFCLK Period
RDY to Clock Set-up Time
200
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
X
Clock to RDY
3.7
X
GPIF Data to Clock Set-up Time
GPIF Data Hold Time
3.2
4.5
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
11.5
15
Clock to CTL Output Propagation Delay
10.7
X
Notes:
20. Dashed lines denote signals with programmable polarity.
21. GPIF asynchronous RDYx signals have a minimum Set-up time of 50 ns when using internal 48-MHz IFCLK.
22. IFCLK must not exceed 48 MHz.
Document #: 38-08032 Rev. *G
Page 39 of 55
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