CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.9
Slave FIFO Asynchronous Write
tWRpwh
SLWR/SLCS#
tWRpwl
tFDH
tSFD
DATA
tXFD
FLAGS
[19]
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram
[23]
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
50
Max.
Unit
ns
t
t
t
t
t
SLWR Pulse LOW
SLWR Pulse HIGH
WRpwl
70
ns
WRpwh
SFD
SLWR to FIFO DATA Set-up Time
FIFO DATA to SLWR Hold Time
10
ns
10
ns
FDH
SLWR to FLAGS Output Propagation Delay
70
ns
XFD
9.10
Slave FIFO Synchronous Packet End Strobe
IFCLK
tPEH
PKTEND
FLAGS
tSPE
tXFLG
[19]
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram
[21]
Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
20.83
14.6
0
Max.
Unit
ns
t
t
t
t
IFCLK Period
IFCLK
PKTEND to Clock Set-up Time
ns
SPE
Clock to PKTEND Hold Time
ns
PEH
XFLG
Clock to FLAGS Output Propagation Delay
9.5
ns
[21]
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
Parameter
Description
Min.
20.83
8.6
Max.
Unit
ns
t
t
t
t
IFCLK Period
200
IFCLK
PKTEND to Clock Set-up Time
ns
SPE
Clock to PKTEND Hold Time
2.5
ns
PEH
XFLG
Clock to FLAGS Output Propagation Delay
13.5
ns
the FIFOs or thereafter. The only consideration is the set-up
time t and the hold time t must be met.
There is no specific timing requirement that needs to be met
for asserting PKTEND pin with regards to asserting SLWR.
PKTEND can be asserted with the last data value clocked into
SPE
PEH
Although there are no specific timing requirement for the
PKTEND assertion, there is a specific corner case condition
Document #: 38-08032 Rev. *G
Page 43 of 55
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