CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.7
Slave FIFO Asynchronous Read
tRDpwh
SLRD
tRDpwl
tXFLG
tXFD
FLAGS
DATA
SLOE
N+1
N
tOEon
tOEoff
[19]
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram
[23]
Table 9-8. Slave FIFO Asynchronous Read Parameters
Parameter Description
SLRD Pulse Width LOW
Min.
50
Max.
Unit
ns
t
t
t
t
t
t
RDpwl
SLRD Pulse Width HIGH
50
ns
RDpwh
XFLG
XFD
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
70
15
ns
ns
10.5
10.5
ns
OEon
ns
OEoff
Note:
23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document #: 38-08032 Rev. *G
Page 41 of 55
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