CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.3
Data Memory Read
tCL
Stretch = 0
[17]
CLKOUT
tAV
tAV
A[15..0]
RD#
tSTBH
tSTBL
tSCSL
CS#
OE#
tSOEL
tDSU
[19
tDH
tACC1
D[7..0]
data in
Stretch = 1
tCL
[17]
CLKOUT
tAV
A[15..0]
RD#
CS#
tDSU
tDH
[19]
tACC1
D[7..0]
data in
Figure 9-2. Data Memory Read Timing Diagram
Table 9-2. Data Memory Read Parameters
Parameter Description
1/CLKOUT Frequency
Min.
Typ.
20.83
41.66
83.2
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
48 MHz
24 MHz
12 MHz
t
CL
t
t
t
t
t
t
t
Delay from Clock to Valid Address
Clock to RD LOW
10.7
11
AV
STBL
STBH
SCSL
SOEL
DSU
Clock to RD HIGH
11
Clock to CS LOW
13
Clock to OE LOW
11.1
Data Set-up to Clock
Data Hold Time
9.6
0
DH
Note:
19. tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
Document #: 38-08032 Rev. *G
Page 37 of 55
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