CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.4
Data Memory Write
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
WR#
CS#
tSCSL
tON1
tOFF1
data out
D[7..0]
Stretch = 1
tCL
CLKOUT
A[15..0]
tAV
WR#
CS#
tON1
tOFF1
data out
D[7..0]
Figure 9-3. Data Memory Write Timing Diagram
Table 9-3. Data Memory Write Parameters
Parameter Description
Min.
Max.
10.7
11.2
11.2
13.0
13.1
13.1
Unit
ns
Notes
t
t
t
t
t
t
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
0
0
0
AV
ns
STBL
STBH
SCSL
ON1
ns
ns
0
0
ns
Clock to Data Hold Time
ns
OFF1
Document #: 38-08032 Rev. *G
Page 38 of 55
CYPRESS [ CYPRESS ]
