PRELIMINARY
CYW54907
Device Output Timing
SDIO device output timing in the SDR modes with clock rates up to 50 MHz is shown by the combination of Figure 27 and Table 50.
Figure 27. SDIO Bus Output Timing (SDR Modes up to 50 MHz)
tCLK
SDIO _CLK
tO D LY
tO H
CM D input
DAT[3:0] input
Table 50. SDIO Bus Output Timing Parameters (SDR Modes up to 50 MHz)
Symbol
tODLY
tOH
Minimum
Maximum
Unit
ns
Comments
–
14.0
–
tCLK ≥ 20 ns CL= 40 pF
Hold time at the tODLY (min.) CL= 15 pF
1.5
ns
17.4 S/PDIF Interface Timing
The S/PDIF protocol embeds the clock and data within a stream of data using a Biphase Mark Code (BMC).
Figure 28 shows the S/PDIF interface timing.
Figure 28. S/PDIF Interface Timing
C lo c k
D a t a
1
0
0
1
1
0
1
0
0
1
0
E n c o d e d ( B M C )
Figure 29 shows the S/PDIF data output timing.
Figure 29. S/PDIF Data Output Timing
tC L K
S P D IF _ O U T
tC R
tC F
tC R
Document Number: 002-19312 Rev. *C
Page 80 of 95
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