PRELIMINARY
CYW54907
17.3.3 SDIO Bus Timing Specifications in SDR Modes
Clock Timing
SDIO clock timing in the SDR modes is shown by the combination of Figure 25 and Table 48.
Figure 25. SDIO Clock Timing (SDR Modes)
tCLK
SDIO_CLK
tCR
tCF
tCR
Table 48. SDIO Bus Clock Timing Parameters (SDR Modes)
Parameter
Symbol
Minimum
Maximum
Unit
ns
Comments
–
tCLK
40
20
–
–
SDR12 mode
SDR25 mode
CCARD = 10 pF
–
–
0.2 × tCLK
70
ns
–
t
CR, tCF
–
ns
Clock duty cycle
30
%
Device Input Timing
SDIO device input timing in the SDR modes is shown by the combination of Figure 26 and Table 49.
Figure 26. SDIO Bus Input Timing (SDR Modes)
SDIO_CLK
tIS
tIH
CMD input
DAT[3:0] input
Table 49. SDIO Bus Input Timing Parameters (SDR Modes)
Symbol
tIS
Minimum
3.00
Maximum
Unit
ns
Comments
–
–
CCARD = 10 pF, VCT = 0.975V
CCARD = 5 pF, VCT = 0.975V
tIH
0.80
ns
Document Number: 002-19312 Rev. *C
Page 79 of 95
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