PRELIMINARY
CYW54907
Table 44. Timing for I2S Transmitters and Receivers
Transmitter
Receiver
Parameter
Lower Limit
Upper Limit
Lower Limit
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Clock period T
Ttr
–
–
–
Ttr
–
Slave mode:
Clock HIGH, tHC
–
–
–
–
0
–
–
0.35Tr
–
–
–
–
–
–
–
–
–
–
0.35Tr
Clock LOW, tLC
0.35Tr
–
0.35Tr
Clock rise time, tRC
Transmitter delay, tdtr
Transmitter hold time, thtr
Receiver setup time, tsr
Receiver hold time, thr
–
–
–
–
–
0.15Ttr
–
–
–
–
–
–
–
0.8T
–
–
–
0.2Tr
0
–
Table 45 provides the I2S_MCLK specification.
Table 45. I2S_MCLK Specification
Parameter
Minimum
Typical
Maximum
Unit
MHz
Frequency range
1
–
–
–
–
–
–
–
–
1
40
–
Frequency accuracy (with respect to the XTAL frequency)
Tuning resolution
ppb
50
1000
–
–
ppb
Tuning range
–
ppm
Tuning step size
10
–
ppm
Tuning rate
1
ppm/ms
ps rms
ps rms
Baseband jitter (100 Hz to 40 kHz)
Wideband jitter (100 Hz to 1 MHz)
–
100
200
–
Figure 22 shows the I2S frame-level timing.
Figure 22. I2S Frame-Level Timing
1/fs
I2S_LRCLK
I2S_SCLK
I/O Data
Left Channel
Right Channel
1 clock
1 clock
1
2
3
n – 2 n – 1
n
1
2
3
n – 2 n – 1
n
MSB
LSB
MSB
LSB
Document Number: 002-19312 Rev. *C
Page 76 of 95
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