PRELIMINARY
CYW54907
17.3.2 SDIO High-Speed Mode Timing
SDIO high-speed (HS) mode timing is shown by the combination of Figure 24 and Table 47.
Figure 24. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Table 47. SDIO Bus Timinga Parameters (High-Speed Mode)
Parameter Symbol
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Minimum
Typical
Maximum
Unit
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
fOD
tWL
tWH
tTLH
tTHL
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
kHz
ns
Clock high time
–
ns
Clock rise time
3
ns
Clock low time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
6
2
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
2.5
–
–
–
–
14
–
ns
ns
pF
Total system capacitance (each line)
CL
40
a. Timing is based on CL 40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
Document Number: 002-19312 Rev. *C
Page 78 of 95
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