PRELIMINARY
CYW54907
Table 51 provides the S/PDIF biphase mark code timing parameters (to be used in conjunction with Figure 29).
Table 51. SPDIF Biphase Mark Code Timing Parameters
Parameter
Symbol
tCLK
CR, tCF
Minimum
Maximum
Unit
Comments
192 kHz sample rate
–
–
40
–
–
ns
ns
t
0.3 × tCLK
–
Duty cycle
–
30
70
%
–
Table 52 provides the S/PDIF biphase mark code sample rate and receiver clock frequency.
Table 52. SPDIF Biphase Mark Code Sample Rate and Receiver Clock Frequency
Parameter
Symbol
Minimum
Maximum
Unit
Comments
Sampling frequency
fS
fCLOCK
–
–
192
25
kHz
192 kHz sample rate maximum.
Component clock
frequency
MHz
Typical is 128 × fS, max is 192 × fS.
Clock is 2× the desired data rate or
2 × 192 kHz × 64 = 24.576 MHz.
Document Number: 002-19312 Rev. *C
Page 81 of 95
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