PRELIMINARY
CYW54907
17.5 SPI Flash Timing
17.5.1 Read-Register Timing
Figure 30 shows the SPI flash extended and quad read-register timing.
Note: Regarding Figure 30: All Read Register commands except Read Lock Register are supported. A Read Nonvolatile Configuration Register operation will output data
starting from the least significant byte.
Figure 30. SPI Flash Read-Register Timing
0
7
8
9
10
11
12
13
14
15
Extended
C
LSB
DQ0
DQ1
Command
High-Z
MSB
LSB
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
0
1
2
3
Quad
C
LSB
LSB
DOUT
DQ[3:0]
Command
DOUT
MSB
DOUT
Don’t care
MSB
Document Number: 002-19312 Rev. *C
Page 82 of 95
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